Importance

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Abstract

A synchronous memory includes a memory cell array with a plurality of memory cells arranged in a matrix, the memory cell array being divided into four banks respectively including a plurality of memory cell arrays therein, the synchronous memory further including a first bus for transferring data from and to the memory cell arrays in the first and the second banks, a second bus for transferring data from and to the memory cell arrays in the third and the fourth banks, and an activating circuit for selectively activating memory cell arrays belong to a single bank of the first to fourth banks so that at least two memory cell arrays within the single bank are simultaneously activated.

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First Claim