System and method for identifying finite state machines and verifying circuit designs

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6487704
SERIAL NO

09076681

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

To identify a finite state machine and verify a circuit design, the invention identifies, in a design description, a set of constructs, a construct in the set of constructs, and an object in the construct. It next identifies a first subset of constructs in the set of constructs which can control a change of a value of the object, and then identifies a second subset of constructs whose values can be changed directly or indirectly by the object. The identifying and storing steps are repeated for all objects in the construct and for all constructs in the set of constructs. A finite state machine is identified by searching for a first object which controls a change of a value of a second object and whose value is also changed directly or indirectly by the second object. This method of identifying finite state machine elements in a design description is used by a test generator which then generates test vectors for exercising the finite state machine elements on a test bench.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddress
CADENCE DESIGN (ISRAEL) II LTD2655 SEELY AVE SAN JOSE CA 95134

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chien, Chiahon Saratoga, CA 5 122
Massey, David Todd Boulder Creek, CA 5 191
McNamara, Michael Santa Clara, CA 28 295
Tan, Chong Guan Saratoga, CA 4 138

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation