LAYOUT DESIGN SYSTEM OF SEMICONDUCTOR IC DEVICE, LAYOUT DESIGN METHOD OF SEMICONDUCTOR IC DEVICE AND COMPUTER-READABLE RECORDING MEDIUM ON WHICH PROGRAMS FOR ALLOWING COMPUTER TO EXECUTE RESPECTIVE MEANS IN THE SYSTEM OR RESPECTIVE STEPS IN THE METHOD ARE RECORDED
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United States of America Patent
Stats
-
Nov 26, 2002
Grant Date -
N/A
app pub date -
Mar 22, 2000
filing date -
Oct 25, 1999
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A floor plan and a cell layout in each of a plurality of blocks are designed. A clock tree is generated in such a manner that the clock skew in each lower level block is minimum. Placement position of a root clock driver and information about an area where the cells can be placed are given to the upper level block. An average delay value of delay values from the root clock driver to a distal buffer is obtained for each block. A flock tree is generated based on these information in such a manner that the clock skew between the higher level block is minimum. If a buffer is newly generated, then its placement position is adjusted based on the cell layout of the lower level block. Wire is distributed in the lower and then in the higher level blocks.
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