Hierarchical location constraints for programmable layouts

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United States of America Patent

PATENT NO 6487708
SERIAL NO

09823047

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Abstract

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Methods for designating target locations for circuit elements to be implemented in a programmable system. A target system is divided into blocks at various levels of hierarchy, with each block within the same higher-level block having a different identifier. A user can specify a desired location for a circuit element at any or all of these levels of hierarchy. Preferably, a desired location is specified using a single location constraint comprising a string of identifiers separated by delimiters. In one embodiment, a uniform coordinate system is applied to all blocks at a given level, even in a non-uniform programmable array. In this embodiment, a non-uniform array of logic blocks is divided into tiles, and a uniform coordinate system is applied to the tiles. Thus, any tile in the array can be addressed using a uniform coordinate system, regardless of the nature of the logic blocks comprising the tile.

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Patent Owner(s)

Patent OwnerAddress
XILINX INC2100 LOGIC DRIVE SAN JOSE CA 95124

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Canaris, John A Albuquerque, NM 2 16

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