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United States of America Patent

PATENT NO 6489204
SERIAL NO

09932727

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Abstract

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Using current technology, the only way to further increase device density is to decrease device pitch. The present invention achieves this by introducing a sidewall doping process that effectively reduces the source width, and hence the pitch. This sidewall doping process also eliminates the need for a source implantation mask while the sidewall spacer facilitates silicide formation at the source, the P body contact, and the polysilicon gate simultaneously. Since the source and P body are fully covered by silicide, the contact number and contact resistance can be minimized. The silicided polysilicon gate has a low sheet resistance of about 4-6 ohm/square, resulting in a higher operating frequency.

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Patent Owner(s)

  • EPISIL TECHNOLOGIES INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Tsui, Bing-Yue Hsinchu, TW 30 366

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