Method and system for identifying configuration circuit addresses in a schematic hierarchy
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United States of America Patent
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Dec 3, 2002
Grant Date -
N/A
app pub date -
Oct 4, 2000
filing date -
Oct 4, 2000
priority date (Note) -
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Abstract
A method and system for automatically identifying configuration cell addresses in a schematic hierarchy is disclosed. In one embodiment of the present invention, a memory cell (e.g., a configuration bit) is identified in a schematic hierarchy. Next, this embodiment determines an address for the memory cell. Then, this embodiment determines a unique name for the memory cell. The name is comprised of a hierarchical logical name and a schematic path name. By traversing the schematic and using logical names, all addresses of configuration bits of a circuit design may be automatically determined. The process is repeated for each memory cell in the schematic. This embodiment stores the unique name of the configuration bit and the address of the configuration bit in a data structure.
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