Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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Dec 10, 2002
Grant Date -
N/A
app pub date -
Sep 22, 2000
filing date -
Sep 22, 2000
priority date (Note) -
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status (Latency Note)
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Abstract
In accordance with the objectives of the invention a new package is provided that is provided with a cavity that is shaped such that more than one semiconductor device can in a vertical direction be mounted in the cavity of the package. The devices that are mounted inside the cavity of the package are separated by separate components of insulation, the overlying devices are electrically interconnected by horizontally positioned solder bumps and vertical interconnect plugs.
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