Low power analog equalizer with variable op-amp gain
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United States of America Patent
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Dec 10, 2002
Grant Date -
N/A
app pub date -
Oct 25, 2001
filing date -
Oct 25, 2001
priority date (Note) -
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Abstract
A low power analog equalizer is disclosed that provides up to twenty decibels (20 dB) of alternating current gain in a single stage of analog signal equalization. The analog equalizer comprises an operational amplifier coupled to two half circuits. Each half circuit comprises an impedance network capable of receiving an analog input voltage and generating a current signal that is inversely proportional to frequency, a variable resistor capable of adjusting the gain of the operational amplifier, and a transistor and an amplifier coupled in a cascode configuration to create a low impedance node at the output of the impedance network. The analog equalizer is fabricated with 0.18 micron CMOS technology and operates at 1.8 volts.
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