Data validity measure for efficient implementation of first-in-first-out memories for multi-processor systems
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United States of America Patent
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Dec 10, 2002
Issued Date -
N/A
app pub date -
Nov 15, 2000
filing date -
May 30, 1997
priority date (Note) -
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Abstract
To reduce FIFO access cycles across a system bus in a multi-processor system in which two processors communicate across a system bus through a FIFO, two separate FIFO descriptors are provided. The first descriptor is maintained by the processor located on-board with the FIFO, and the second descriptor is maintained by an off-board processor which communicates with the FIFO across the bus. When one processor performs a FIFO operation, the processor updates the other processor's descriptor via a memory access across the bus. Additionally, one module passes credits to the other to indicate that the latter has permission to perform a plurality of FIFO operations consecutively. In one embodiment a special non-valid data value is used to indicate an empty FIFO position.
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