Importance

Loading Importance Indicators...

Abstract

A semiconductor memory device which includes a set of interface terminals to receive a plurality of control signals which specify that the memory device receive a first set of data bits and a second set of data bits. The plurality of control signals further specify that the memory device precharge sense amplifiers used in writing the first set of data bits to an array of memory cells, and precharge sense amplifiers used in writing the second set of data bits to the array of memory cells. The memory device further includes a mask terminal to receive a first mask bit during a first half of a clock cycle of an external clock signal, the first mask bit to indicate whether to write the first set of data bits to the array. The mask terminal further receives a second mask bit during a second half of the clock cycle of the external clock signal, the second mask bit to indicate whether to write the second set of data bits to the array.

Loading the Abstract Image...

First Claim