Apparatus and method for virtual address aliasing and multiple page size support in a computer system having a prevalidated cache
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United States of America Patent
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Dec 10, 2002
Grant Date -
N/A
app pub date -
Dec 17, 1999
filing date -
Dec 17, 1999
priority date (Note) -
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Abstract
A computer micro-architecture employing a prevalidated cache tag design includes circuitry to support virtual address aliasing and multiple page sizes. Support for various levels of address aliasing are provided through a physical address CAM, page size mask compares and a column copy tag function. Also supported are address aliasing that invalidates aliased lines, address aliasing with TLB entries with the same page sizes, and address aliasing the TLB entries of different sizes. Multiple page sizes are supported with extensions to the prevalidated cache tag design by adding page size mask RAMs and virtual and physical address RAMs.
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