Integrated circuit block model representation hierarchical handling of timing exceptions
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United States of America Patent
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Dec 10, 2002
Grant Date -
N/A
app pub date -
Jun 20, 2001
filing date -
Jun 20, 2001
priority date (Note) -
Expired
status (Latency Note)
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Abstract
In a block model abstraction of an integrated circuit developed from a hierarchal netlist, the hierarchal handling of timing exceptions is accomplished by selecting certain nodes not viewable at the top level in accordance with a set of rules, and raising these nodes to the top level so that defined timing exceptions may be applied. The timing model is next generated, and exception signatures created for paths between the selected nodes. Signatures are then removed from paths were such signature would not otherwise be valid.
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