Control signal generator for an overvoltage-tolerant interface circuit on a low voltage process
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United States of America Patent
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Dec 17, 2002
Grant Date -
N/A
app pub date -
May 9, 2001
filing date -
May 13, 2000
priority date (Note) -
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Abstract
A circuit that may be configured to provide a first well bias voltage to the output buffer when the output buffer is in a first mode and to provide a second well bias voltage to the output buffer when the output buffer is in a second mode. The first well bias voltage and the second well bias voltage may be used to maintain a reverse bias in diffusion wells used for electrical isolation of transistors.
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