Method and apparatus for fast loading of texture data into a tiled memory
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United States of America Patent
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Dec 17, 2002
Grant Date -
N/A
app pub date -
Dec 30, 1999
filing date -
Dec 30, 1999
priority date (Note) -
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Abstract
An apparatus for loading texture data into a tiled memory includes state machine logic to generate a sequence of addresses for writing a cacheline of texture data into the tiled memory according to Y-major tiling. The cacheline comprises quadwords (QWs) 0-3, wherein the sequence corresponds to an ordering of the QWs 0-3, ordered as either: (a) QW0, QW1, QW2, QW3; (b) QW1, QW0, QW3, QW2; (c) QW2, QW3, QW0, QW1; or (d) QW3, QW2, QW1, QW0, depending upon a starting address.
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