Digital FM receiver employing combined sample-and-hold and integrate-and-dump detectors for improved bit error rates
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Dec 17, 2002
Grant Date -
N/A
app pub date -
Nov 30, 1999
filing date -
Nov 30, 1999
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A narrow-band digital frequency-modulation (FM) limiter-discriminator (LD) receiver with two independent detectors that combine to remove most of the bit errors caused by FM-clicks in an encoded channel. The output of the LD circuit is presented to a sample-and-hold (S&H) detector and to an integrate and dump (I&D) detector. Because the S&H and I&D detector outputs are offset in time by one-half bit and they are not entirely correlated, an error in one does not necessarily imply an error in the other. Using convolutional coding and Viterbi decoding, with threshold-compensation of the I&D detector output and threshold- or envelope-compensation of the S&H detector output, averaging the two compensated detector signals improves the receiver bit error rate (BER) performance by more than 3 dB over the soft-decision thresholded I&D detector alone, which until now was believed to be optimum in the art.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully