Built-in self repair circuit with pause for data retention coverage
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United States of America Patent
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Dec 17, 2002
Grant Date -
N/A
app pub date -
Oct 25, 1999
filing date -
Oct 25, 1999
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A single-chip integrated circuit includes a memory array, a built-in self test circuit and a pause circuit. The built-in self test circuit is coupled to the memory array and is adapted to execute a sequence of write and read operations on the memory array. The pause circuit is coupled to and activated by the built-in self test circuit. When activated, the pause circuit pauses the sequence of write and read operations for a pause time period.
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