Distributed interface for parallel testing of multiple devices using a single tester channel
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United States of America Patent
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Dec 24, 2002
Grant Date -
N/A
app pub date -
Mar 1, 1999
filing date -
Mar 1, 1999
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A system for testing a number of integrated circuit (IC) devices under test (DUTs) having interface circuitry coupled to a single or multi-channel tester for receiving data values from the tester and providing error information concerning the DUTs. The interface circuitry forwards data values (received from the tester over a single channel) to a number of DUTs in parallel. The circuitry performs comparisons using data values read from the DUTs, and in response generates error values indicative of the comparison. The error values may then be returned to the tester over the same or a different channel.
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