Method and apparatus for debugging an integrated circuit
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United States of America Patent
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Dec 24, 2002
Issued Date -
N/A
app pub date -
Apr 12, 2000
filing date -
Feb 24, 1989
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An integrated circuit having a normal mode for operating under normal operating conditions and a debug mode for operating to test and debug the integrated circuit. The integrated circuit includes a plurality of output pins that carry a first plurality of signals in the normal mode and carry a second plurality of signals in the debug mode. In one embodiment, the integrated circuit embodies a microprocessor. The microprocessor may include logic circuitry for enabling the second plurality of signals to be output from a multiplexer to the output pins in response to a predetermined event, such as a hit in an associated memory unit.
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