Arrangement relating to electronic circuitry
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United States of America Patent
Stats
-
Dec 31, 2002
Grant Date -
Jun 14, 2001
app pub date -
Dec 8, 2000
filing date -
Dec 10, 1999
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
The present invention relates to an arrangement in a multilayered electronic circuit. In a transition between two planar transmission lines, a compensating element is used to keep the average capacitance per length unit more constant during the transition. A via conductor the passes near an edge of a planar conductor pattern, the via conductor and the planar conductor having a mutual capacitive coupling within a predetermined range. A compensating conductor is formed between the planar conductor and the via conductor, which conductor is connected to the planar conductor by a compensating via. If the segment of the via conductor which belongs to the same via hole pattern as the compensating via is displaced, the compensating via is also displaced. The compensating planar pattern is then disconnected from the planar conductor. This improves yield in a given multilayer process.
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