Loadable divide-by-N with fixed duty cycle
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United States of America Patent
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Dec 31, 2002
Grant Date -
N/A
app pub date -
Jun 30, 2000
filing date -
Jun 30, 2000
priority date (Note) -
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Abstract
A circuit configured to generate an output signal having a first frequency in response to a clock signal having a second frequency. The output signal may be in a first state and a second state for an equal number of half-cycles of the clock signal.
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