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Abstract

An electronic circuit design environmentally constrained test generation system provides a corrector mechanism that filters the input signals to the design under verification (DUV) and ensures that inputs signals to the DUV are within the given environmental constraints that describe the limitations on the permissible inputs to the DUV. Both combinational and temporal constraints can be handled by the corrector, which consists of a new element, a mapper, and an observer. The mapper looks at the observer's state and external test sequence input value and changes non-compliant test sequence input to the DUV to place the DUV in a legal state if the input would place it on a track to an illegal state, thereby constraining the inputs to the normal expected operating environment of the DUV. An illegal state is a state from which the violation of at least one constraint is unavoidable. A feedback loop from the DUV to the observer may be implemented using constraints that rely upon the DUV's state.

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First Claim