Integrated circuit that includes a field-programmable gate array and a hard gate array having the same underlying structure
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jan 7, 2003
Issued Date -
N/A
app pub date -
Oct 16, 2000
filing date -
May 25, 1999
priority date (Note) -
Expired
status (Latency Note)
A preliminary load of PAIR data current through [] has been loaded. Any more recent PAIR data will be loaded within twenty-four hours. |
PAIR data current through []
A preliminary load of cached data will be loaded soon.
Any more recent PAIR data will be loaded within twenty-four hours.
Next PAIR Update Scheduled on [ ] |
Importance
US Family Size
|
Non-US Coverage
|
Patent Longevity
|
Forward Citations
|
Abstract
An integrated circuit (IC) includes both a field-programmable gate array (FPGA) and a hard array (HA). The FPGA includes a first set of functional groups that each include an underlying logic structure and memory cells for programming the underlying logic structure, a first set of routing buses, and a first set of routing interconnect areas that provide interconnections between the first set of functional groups and the first set of routing buses. The first set of routing interconnect areas includes transistors and memory cells for programming the interconnections. The HA includes a second set of functional groups that is equal in number to the first set of functional groups and that are arranged like the first set of functional groups. Each functional group in the second set of functional groups includes an underlying logic structure that is like the underlying logic structure of the first set of functional groups but which does not include memory cells for programming the underlying logic structure. The HA also includes a second set of routing buses that are arranged like the first set of routing buses and a second set of routing interconnect areas that are arranged like the first set of routing interconnect areas but which do not include transistors and memory cells for programming interconnections.
First Claim
Family
- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
- ACTEL CORPORATION
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Feng, Sheng | Cupertino, CA | 46 | 1511 |
Huang, Eddy Chieh | San Jose, CA | 5 | 407 |
Lien, Jung-Cheun | San Jose, CA | 41 | 2100 |
Sun, Chung-yuan | San Jose, CA | 22 | 1252 |
Cited Art Landscape
- No Cited Art to Display
Patent Citation Ranking
Forward Cite Landscape
- No Forward Cites to Display
Maintenance Fees
Fee | Large entity fee | small entity fee | micro entity fee | due date |
---|
Fee | Large entity fee | small entity fee | micro entity fee |
---|---|---|---|
Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
Full Text
Legal Events
Matter Detail
Update Public Data Dismiss Edit SaveRenewals Detail
Edit SaveNote
The template below is formatted to ensure compatibility with our system.
Provide tags with | separated like (tags1|tags2).
Maximum length is 128 characters for Customer Application No
Mandatory Fields * - 'MatterType','AppType','Country','Title','SerialNo'.
Acceptable Date Format - 'MM/DD/YYYY'.
Acceptable Filing/App Types -
- Continuation/Divisional
- Original
- Paris Convention
- PCT National
- With Priority
- EP Validation
- Provisional Conversion
- Reissue
- Provisional
- Foreign Extension
Acceptable Status -
- Pending
- Abandoned
- Unfiled
- Expired
- Granted
Acceptable Matter Types -
- Patent
- Utility Model
- Supplemental Protection Certificate
- Design
- Inventor Certificate
- Plant
- Statutory Invention Reg
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Success
E-mail has been sent successfully.
Failure
Some error occured while sending email. Please check e-mail and try again!
PAIR load has been initiated
A preliminary load of cached data will be loaded soon. Current PAIR data will be loaded within twenty four hours.
File History PDF
Thank you for your purchase! The File Wrapper for Patent Number 6504398 will be available within the next 24 hours.
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully
Important Notes on Latency of Status data
Please note there is up to 60 days of latency in this Status indicator for certain status conditions. You can obtain up-to-date Status indicator readings by ordering PAIR for the file.
An application with the status "Published" (which means it is pending) may be recently abandoned, but not yet updated to reflect its abandoned status. However, an application filed less than one year ago is unlikely to be abandoned.
A patent with the status "Granted" may be recently expired, but not yet updated to reflect its expired status. However, it is highly unlikely a patent less than 3.5 years old would be expired.
An application with the status "Abandoned" is almost always current, but there is a small chance it was recently revived and the status not yet updated.
Important Note on Priority Date data
This priority date is an estimated earliest priority date and is purely an estimation. This date should not be taken as legal conclusion. No representations are made as to the accuracy of the date listed. Please consult a legal professional before relying on this date.
We are sorry but your current selection exceeds the maximum number of portfolios (0) for this membership level. Upgrade to our Level for up to -1 portfolios!.