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Abstract

A semiconductor erasable programmable read-only memory (EPROM) device provided for operation with a plurality of first level sense-circuits. The EPROM memory device includes an EPROM memory cell array having a plurality of first-direction first-level bit lines disposed in a parallel manner along a first direction. The EPROM memory device further includes a plurality of word lines intersected with the first-direction first-level bit lines. The EPROM memory cell array further includes a plurality of EPROM memory cells wherein each of the plurality of memory cells being coupled between one of the first-direction first level bit lines and one of the word lines for storing data therein. And, the EPROM memory device further includes a plurality of different-direction first level bit-lines disposed along at least one different direction different from the first direction. Each of the different-direction first-level bit lines connected between a plurality of the first-direction first level bit lines and one of the first level sense-circuits.

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First Claim