Configurable DDR write-channel phase advance and delay capability
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United States of America Patent
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-
Jan 7, 2003
Grant Date -
N/A
app pub date -
Aug 9, 2001
filing date -
Aug 9, 2001
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
The phase of a memory clock signal is adjusted by advancing and/or delaying the phase. A configuration register is used to determine the phase adjustment of the memory clock signal. The value of the configuration register can be changed through software. This flexible phase adjustment technique is valuable in meeting various timing requirements in a source synchronous memory controller.
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