Importance

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Abstract

A method of generating a priority address using a priority encoder that includes the steps of: (1) providing a plurality of match signals from a CAM cell memory array to the priority encoder, (2) generating a most significant address bit of the priority address in response to a first set of the match signals, and (3) generating a least significant address bit of the priority address in response to the most significant address bit and a second set of the match signals. In one embodiment, step (3) is implemented by splitting the determination of the least significant address bit into two separate determinations, and the using the most significant address bit to select the result of one of these two separate determinations. Using the most significant address bit to help determine the least significant address bit significantly increases the speed of determining the least significant address bit, thereby increasing the overall speed of the priority encoder. Another embodiment includes a priority encoder that includes a first address generator for generating the most significant address bit in response to the first set of match signals, and a second address generator for generating the least significant address bit in response to the second set of match signals and the most significant address bit.

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First Claim