Processor including efficient fetch mechanism for L0 and L1 caches
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United States of America Patent
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-
Jan 7, 2003
Grant Date -
N/A
app pub date -
Jan 29, 2002
filing date -
Nov 17, 1997
priority date (Note) -
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status (Latency Note)
Importance
Abstract
A processor includes a first instruction cache, a second instruction cache, a return stack, and a fetch unit. The return stack is configured to store return addresses corresponding to call instructions. The return stack is configured to output a first return address from a top of the return stack and a second return address which is next to the top of the return stack. The fetch unit is coupled to the first instruction cache, the second instruction cache, and the return stack, and is configured to convey the first return address to the first instruction cache responsive to a return instruction. Additionally, the fetch unit is configured to convey the second return address to the second instruction cache responsive to the return instruction.
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