Fault tolerant parity generation

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United States of America Patent

PATENT NO 6505321
SERIAL NO

09315437

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A method and system for providing parity protection to data. The method and system includes transmitting pairs of groups of bits. Each one of the groups of bits has bits representing the data and a parity bit. The parity sense of one of the pair of groups of bits is opposite to the parity sense of the other one of the pair of groups of bits. The transmitted pair of groups of bits are received. The received pair of groups of bits are parity checked to determine whether the parity sense of one of the received pair of groups, of bits is opposite to the parity sense of the other one of the received pair of groups of bits. With such an arrangement, a failure in the data driver or data receiver which causes the output of all bits produced by such driver to assume the same logic state can be detected because the received pair of groups of bits will have, with such failure, the same parity sense. The method and system also includes transmitting successive groups of bits in response to clock pulses. With such an arrangement, a method and system are provided for detecting a failure in the clock pulses because such a failure will result in the absence of an alternating parity sense in the successively received groups of bits.

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Patent Owner(s)

Patent OwnerAddress
EMC IP HOLDING COMPANY LLC176 SOUTH STREET HOPKINTON MA 01748

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
MacLellan, Christopher S Norwood, MA 45 702
Walton, John K Mendon, MA 48 714

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