Flash EEPROM with integrated device for limiting the erase source voltage
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United States of America Patent
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Jan 14, 2003
Grant Date -
N/A
app pub date -
Jul 31, 1996
filing date -
Aug 2, 1995
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A flash EEPROM having an array of memory cells which include a common source line connecting together source electrodes of the memory cells. A resistive feedback element is coupled in series between the common source line and a positive potential when the memory cells must be electrically erased. The Flash EEPROM includes a voltage limiting circuit coupled to the common source line for limiting the potential of the common source line to be prescribed maximum value lower than the positive potential.
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