Efficient arrangement of interconnection resources on programmable logic devices
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jan 14, 2003
Grant Date -
N/A
app pub date -
Jul 17, 2001
filing date -
Nov 18, 1998
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
Interconnection block arrangements for selectively interconnecting logic on a programmable logic device is provided. Programmable logic connectors within the interconnection blocks may be programmed to route signals between the various conductors on the device and to route signals from various logic regions on the device to the various conductors. The interconnection blocks are arranged to optimize the use of metallization resources and to increase interconnectivity and logic density.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully