Nonvolatile semiconductor memory device having ferroelectric capacitors

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6507510
APP PUB NO 20020021579A1
SERIAL NO

09902168

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Abstract

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A memory cell array is constructed by a plurality of sub-arrays which include a plurality of sub-word lines, a plurality of bit lines, a plurality of plate lines and a plurality of memory cell blocks, plural ones of the sub-arrays being arranged in the sub-word line direction, a plurality of sub-row decoders provided between the plurality of respective sub-arrays, for driving the sub-word lines, a main row decoder disposed on one-end side of the plurality of sub-arrays in the sub-word line direction, and a plurality of main-block selecting lines for respectively supplying outputs of the main row decoder to the sub-row decoders. The main-block selecting lines for connecting the main row decoder to the sub-row decoders are formed of the same interconnection layer as the plate lines and metal interconnections used between the memory cells in the cell block.

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Patent Owner(s)

Patent OwnerAddress
TOSHIBA MEMORY CORPORATION1-1 SHIBAURA 1-CHOME MINATO-KU TOKYO 105-0023

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Takashima, Daisaburo Yokohama, JP 247 3491

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