Method and apparatus for reducing DC offset
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United States of America Patent
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Jan 21, 2003
Grant Date -
Jul 25, 2002
app pub date -
Jan 23, 2001
filing date -
Jan 23, 2001
priority date (Note) -
In Force
status (Latency Note)
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Abstract
Various circuits and methods provide for dc offset reduction that is effective under varying circuit and signal conditions. The offset signal is first sampled and stored, and then subtracted from the signal path via a programmable transconductance amplifier that is placed in a feedback loop during offset reduction. By designing the transconductance amplifier to have programmable gain, the offset reduction technique is capable of compensating for variations in the magnitude of the offset signal. In one embodiment, an amplifier is placed in the feedback path in series with the programmable transconductance amplifier to optimize the trade off between noise and accuracy of offset reduction.
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