Importance

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Abstract

A method of fabricating a thin film transistor (TFT) assembly having a plurality of array lines, a plurality of pads, a plurality of link lines connecting the pads to the array lines, an insulating layer, and an electrode pattern formed on a substrate, and further having short-preventing structures for preventing electrical shorts between the pads and the link lines. The method includes the steps of forming the plurality of pads on the substrata, depositing the insulating layer on the substrate including over the pads, etching the insulating layer, to form contact holes, and etching the insulating layer between the adjacent pads to expose a surface of the substrate to prevent a short between the adjacent pads from occurring, and forming the electrode pattern on the insulating layer by depositing and patterning an electrode layer such that the electrode pattern contacts the pads through the contact holes formed in the insulating layer. The steps of etching the insulating layer between the adjacent pads is performed concurrently with the etching step for forming the contact holes. In addition, the areas between adjacent pads are further etched concurrently with the step of etching the electrode layer.

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First Claim