Configurable memory for programmable logic circuits
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United States of America Patent
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Jan 28, 2003
Issued Date -
N/A
app pub date -
Dec 18, 2001
filing date -
Dec 30, 1999
priority date (Note) -
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Abstract
An apparatus comprising a memory device and a programmable logic device. The memory device may be configured to (i) connect to a first bus and a second bus and (ii) operate in one or more modes in response to one or more control signals. The programmable logic device may be configured to generate the control signals.
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