Shared sense amplifier driver technique for dynamic random access memories exhibiting improved write recovery time
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United States of America Patent
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Feb 4, 2003
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N/A
app pub date -
Jan 4, 2002
filing date -
Jan 4, 2002
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Abstract
A shared sense amplifier driver technique for integrated circuit devices including an array of memory cells comprises a plurality of sense amplifiers couplable to the memory cells with each of the sense amplifiers having an associated pull-up and pull-down switching device respectively coupled to a first and second latch node thereof. A first subset of the plurality of sense amplifiers have their first latch node (e.g. latch P-channel 'LP') electrically coupled and a second differing number subset of the plurality of sense amplifiers have their second latch node (e.g. latch N-channel 'LN') electrically coupled. By sharing the selected LP and LN nodes with more than one sense amplifier in a column, 'write' recovery time can be significantly improved over that of conventional layouts and designs.
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