Processor executing unpack instruction to interleave data elements from two packed data
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United States of America Patent
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-
Feb 4, 2003
Issued Date -
N/A
app pub date -
Sep 8, 2000
filing date -
Dec 2, 1994
priority date (Note) -
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status (Latency Note)
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Abstract
An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.
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