Partitioning placement method using diagonal cutlines

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United States of America Patent

PATENT NO 6516455
SERIAL NO

09854182

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Abstract

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Some embodiments of the invention are placers that use diagonal lines in calculating the cost of potential placement configurations. For instance, some embodiments estimate the wirelength cost of a placement configuration by (1) identifying, for each net list, a bounding box that encloses all the circuit elements of the net, (2) computing an attribute of each bounding box by using a line that can be completely or partially diagonal, and (3) computing the wirelength cost estimate based on the computed attributes. To estimate the wirelength cost of different placement configurations, other embodiments construct connection graphs that model the net interconnect topologies. These connection graphs can have edges that are completely or partially diagonal. Other embodiments use diagonal lines to measure congestion costs of potential placement configurations. For instance, some placers use diagonal lines as cut lines that divide the IC layout into regions. These placers then generate congestion-cost estimates by measuring the number of nets cut by the diagonal cut lines.

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Patent Owner(s)

Patent OwnerAddress
CADENCE DESIGN SYSTEMS INC A DELAWARE CORPORATION2655 SEELY AVE BUILDING 5 MS 5B1 SAN JOSE CA 95134

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ganley, Joseph L Vienna, VA 23 383
Teig, Steven Menlo Park, CA 333 6577

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