Input/output architecture for efficient configuration of programmable input/output cells
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United States of America Patent
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Feb 11, 2003
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N/A
app pub date -
Sep 21, 2000
filing date -
Sep 21, 2000
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Abstract
A programmable input/output memory architecture. The programmable input/output memory cells are disposed in two segments about the periphery of the chip. Each segment has two data buses for separate reading and writing of the configuration register. Each cell is selected and configured according to user specifications. Corresponding memory cells from each segment share the same select line, therefore two bytes of configuration data are accessed together and the data is propagated through both segments approximately concurrently thereby reducing propagation delay.
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