One-time programmable logic device
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United States of America Patent
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Feb 11, 2003
Grant Date -
N/A
app pub date -
Aug 24, 2000
filing date -
Aug 31, 1999
priority date (Note) -
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status (Latency Note)
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Abstract
An integrated circuit is provided, in which a one-time programmable logic device disables writing to a storage device on the user side once a current is passed therethrough. The integrated circuit has a flash memory operating as a storage device to/from which writing/erasure is possible when a read/write enable port is in a high level. When a power supply is applied to an external power supply input terminal, a fuse having a polysilicon interconnection pattern is blown after a set time period by the output of a step up regulator circuit. After the fuse is blown, the input of a buffer is fixed to a low level through a resistor, so that the read/write enable port of the flash memory as the output of an AND circuit is fixed to a low level and the flash memory becomes a read only memory.
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