Configuration bits layout

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United States of America Patent

PATENT NO 6519674
SERIAL NO

09507337

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Abstract

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A configuration bit layout for a reconfigurable chip includes address bits stored along with configuration bits. The blocks of data are loaded onto the reconfigurable chip from an external memory and the address information is decoded to load the configuration bits onto the correct locations in the reconfigurable chip. In this way, configuration data need not be stored sequentially in the external memory. Configurations can be allocated into different slices of the reconfigurable chip as well.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATION2200 MISSION COLLEGE BOULEVARD SANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Dakhil, Dani Campbell, CA 1 94
Lam, Peter Shing Fai Santa Clara, CA 3 182
Shyr, Jin-sheng Cupertino, CA 3 246

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