Importance

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Abstract

A high speed programmable ER computational engine that is based on a micro-programmed control unit and a register intensive pipelined datapath that removes the need for having an instruction set interpreter includes a data path unit operably coupled to directly receive datapath control words from a control unit. The control unit includes memory and an address unit, where the memory stores the data path control words, which relate to a computational algorithm. The address unit receives input (e.g., begin an ER calculation) from an external source, where the input causes at least some of the data path control words to be retrieved from the memory. The data path unit includes a pair of register files, a plurality of floating point units, and data flow coupling. The pair of register files operate in a double buffering manner such that one of the register files is receiving parameters (e.g., data rate information of a connection) for subsequent computation while the other is used for a current computation.

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First Claim