US Patent No: 6,519,753

Number of patents in Portfolio can not be more than 2000

Programmable device with an embedded portion for receiving a standard circuit design

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Importance

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Abstract

A programmable device, such as a field programmable gate array, includes a main field that is programmable by the user and at least one embedded portion that is reserved to be programmed with a standard circuit design that is configured, for example, by the manufacturer. The embedded portion is similar to the main field, i.e., it has the same programmable structure, however, the embedded portion is not accessible to the user. In some embodiments, the embedded portion may be pre-programmed with the standard circuit design and in other embodiments the embedded portion is programmed while the user programs the main field. The programmable device may also include signature bits that are used by the programming unit to identify the programmable device as having the embedded portion and which standard circuit design to program into the embedded portion. The signature bit may be programmed after the manufacture of the programmable device or may be hard wired during the manufacture of the device. The programming unit recognizes the configuration of the signature bits and restricts access to embedded portion based on the configuration.

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First Claim

Related Publications

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Patent Owner(s)

Patent OwnerAddressTotal Patents
QUICKLOGIC CORPORATIONSUNNYVALE, CA102

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ahuja, Atul Mountain View, CA 1 42
Ang, Roger Fremont, CA 1 42
Borkovic, Drazen Mountain View, CA 11 85
Chan, Andrew K Palo Alto, CA 49 1510
Lulla, Mukesh T Fremont, CA 4 155
Small, Brian D Portland, OR 2 48
Tralka, Charles C San Jose, CA 1 42
Yee, Kevin K San Jose, CA 4 151

Cited Art

Patent Info (Count) # Cites Year
 
QUICKLOGIC CORPORATION (6)
5,544,070 Programmed programmable device and method for programming antifuses of a programmable device 31 1992
5,526,276 Select set-based technology mapping method and apparatus 54 1994
5,424,655 Programmable application specific integrated circuit employing antifuses and methods therefor 45 1994
5,552,720 Method for simultaneous programming of multiple antifuses 8 1994
5,729,468 Reducing propagation delays in a programmable device 3 1995
5,661,412 Reducing programming time of a field programmable gate array employing antifuses 10 1995
 
LATTICE SEMICONDUCTOR CORPORATION (2)
5,237,218 Structure and method for multiplexing pins for in-system programming 77 1991
6,211,695 FPGA integrated circuit having embedded SRAM memory blocks with registered address and data input sections 12 1999
 
CAMBRIDGE SILICON RADIO LIMITED (1)
6,311,263 Data processing circuits and interfaces 15 1997
 
INTELLECTUAL VENTURES II LLC (1)
5,687,325 Application specific field programmable gate array 223 1996
 
INTELLON CORPORATION (1)
6,044,453 User programmable circuit and method for data processing apparatus using a self-timed asynchronous control structure 12 1997

Patent Citation Ranking

Forward Cites

Patent Info (Count) # Cites Year
 
XILINX, INC. (34)
6,629,308 Method for managing database models for reduced programmable logic device components 128 2000
7,076,595 Programmable logic device including programmable interface core and central processing unit 49 2001
6,798,239 Programmable gate array having interconnecting logic to support embedded fixed logic circuitry 26 2001
6,996,758 Apparatus for testing an interconnecting logic fabric 18 2001
6,983,405 Method and apparatus for testing circuitry embedded within a field programmable gate array 14 2001
6,886,092 Custom code processing in PGA by providing instructions from fixed logic processor portion to programmable dedicated processor portion 56 2001
6,781,407 FPGA and embedded circuitry initialization and processing 13 2002
6,820,248 Method and apparatus for routing interconnects to devices with dissimilar pitches 3 2002
6,976,160 Method and system for controlling default values of flip-flops in PGA/ASIC-based designs 21 2002
6,754,882 Method and system for creating a customized support package for an FPGA-based system-on-chip (SoC) 17 2002
7,007,121 Method and apparatus for synchronized buses 3 2002
6,934,922 Timing performance analysis 10 2002
7,111,217 Method and system for flexibly nesting JTAG TAP controllers for FPGA-based system-on-chip (SoC) 9 2002
6,839,874 Method and apparatus for testing an embedded device 17 2002
7,187,709 High speed configurable transceiver architecture 7 2002
7,111,220 Network physical layer with embedded multi-standard CRC generator 6 2002
7,088,767 Method and apparatus for operating a transceiver in different data rates 5 2002
6,961,919 Method of designing integrated circuit having both configurable and fixed logic circuitry 10 2002
6,772,405 Insertable block tile for interconnecting to a device embedded in an integrated circuit 5 2002
7,085,973 Testing address lines of a memory controller 3 2002
7,099,426 Flexible channel bonding and clock correction operations on a multi-block data path 8 2002
7,092,865 Method and apparatus for timing modeling 7 2002
7,379,855 Method and apparatus for timing modeling 4 2002
7,421,014 Channel bonding of a plurality of multi-gigabit transceivers 1 2003
7,080,300 Testing a programmable logic device with embedded fixed logic using a scan chain 21 2004
7,552,415 Method and system for creating a customized support package for an FPGA-based system-on-chip (SoC) 5 2004
6,996,796 Method and system for creating a customized support package for an FPGA-based system-on-chip (SoC) 7 2004
7,420,392 Programmable gate array and embedded circuitry initialization and processing 5 2004
7,194,600 Method and apparatus for processing data with a programmable gate array using fixed and programmable processors 5 2005
7,254,794 Timing performance analysis 2 2005
7,539,848 Configurable logic fabric including two fixed logic processors with individual interface to receive availability signal from custom operation code configured processor 3 2005
7,406,557 Programmable logic device including programmable interface core and central processing unit 2 2006
7,266,632 Programmable logic device including programmable interface core and central processing unit 11 2006
7,526,689 Testing address lines of a memory controller 1 2006
 
ALTERA CORPORATION (3)
7,058,920 Methods for designing PLD architectures for flexible placement of IP function blocks 3 2003
7,584,447 PLD architecture for flexible placement of IP function blocks 1 2005
8,201,129 PLD architecture for flexible placement of IP function blocks 0 2009
 
ACTEL CORPORATION (2)
7,111,272 Parallel programmable antifuse field programmable gate array device (FPGA) and a method for programming and testing an antifuse FPGA 2 2004
7,549,138 Parallel programmable antifuse field programmable gate array device (FPGA) and a method for programming and testing an antifuse FPGA 0 2007
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (1)
7,045,472 Method and apparatus for selectively altering dielectric properties of localized semiconductor device regions 3 2004
 
QUICKLOGIC CORPORATION (1)
7,482,834 Programmable multiplexer 0 2006
 
OTHER [CHECK PATENT PROFILE FOR ASSIGNMENT INFORMATION] (1)
8,407,649 PLD architecture for flexible placement of IP function blocks 0 2012

Maintenance Fees

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