Method and apparatus for properly disabling high current parts in a parallel test environment
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United States of America Patent
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Feb 18, 2003
Grant Date -
Apr 25, 2002
app pub date -
Jul 5, 2001
filing date -
Jan 26, 1999
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A parallel test system and method for testing integrated circuit devices which can reliably prevent devices that should not be active due to a blown fuse from generating random data signals which can adversely impact the test results of other chips being tested are disclosed. The state of each fuse that protects a respective socket on a test board is determined by a controller, such as an Application Specific Integrated Circuit (ASIC), built onto the test board. When it is determined that a specific fuse is open, i.e., the fuse has blown due to a high current condition, the device inserted into the socket protected by the fuse will have its I/O lines disabled by the controller, thereby effectively shutting off the device completely and preventing it from generating and transmitting random data to the test device.
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