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Abstract

A multiplication accumulation circuit (abbreviated as 'MAC') has five input buses that carry signals for operands A, B, C, D and E, a control bus that carries signals for controlling the operations performed on the received operands, and an output bus that carries a signal generated by the MAC. Each of operands A, B, C and D can be four different operands that are used as follows by the MAC: (1) to perform two multiplications simultaneously, and (2) to perform an addition of the products of the two multiplications and the fifth operand E, e.g. generate on the output bus a signal of value A*C+B*D+E. Alternatively, operands A and B can be, respectively, the upper and lower halves of a first double word to be used as a multiplicand. Similarly, operands C and D can be the upper and lower halves of a second double word to be used as a multiplier. In this case, the four operands A, B, C and D are used as follows by the MAC: (1) to perform a single multiplication of the first double word with the second double word, and (2) to perform an addition of the product of the double word multiplication, and the fifth operand E, e.g. generate on the output bus a signal of value [A,B]*[C,D]+E.

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First Claim