Cache line replacement policy enhancement to avoid memory page thrashing

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6523092
SERIAL NO

09675765

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

A method for a cache line replacement policy enhancement to avoid memory page thrashing. The method of one embodiment comprises comparing a memory request address with cache tags to determine if any cache entry in set `n` can match the address. The address is masked to determine if a thrash condition exists. Allocation to set `n` is discouraged if a thrash condition is present.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATION2200 MISSION COLLEGE BOULEVARD SANTA CLARA CA 95054

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Fanning, Blaise B El Dorado Hills, CA 21 401

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation