Stereolithographic method for applying materials to electronic component substrates and resulting structures

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United States of America Patent

PATENT NO 6524346
SERIAL NO

09259143

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A stereolithographic method of applying material to preformed electronic components with a high degree of precision, and resulting structures. A substrate used for effecting electrical testing of semiconductor dice or a carrier substrate for same may be provided with a protective structure in the form of at least one layer or segment of dielectric material having a controlled thickness or depth. The layer or segment may include precisely sized, shaped and located apertures through which conductive terminals on the surface of the substrate may be accessed. Dielectric material may also be employed as a structure to mechanically align the die with the substrate for proper communication of conductive connective elements projecting from a die with the substrate terminals, either in the form of the apertures in the dielectric material layer or segment on the substrate to partially receive the conductive connective elements, an alignment structure comprising upwardly-projecting alignment elements adjacent or bracketing an intended die location on the substrate, or both.

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Patent Owner(s)

  • CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Farnworth, Warren M Nampa, ID 855 33423

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