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Abstract

A fixed-length delay generation circuit comprises a first variable delay circuit (VDC), a clock generation circuit, a VDC group including one or more second VDCs, and a delay controller. The clock signal is input to a second VDC disposed at the initial stage in the VDC group. The delay controller outputs a signal by which delay amount in the first and second VDCs are made smaller when a difference between phases of a delay clock signal output from the VDC group and of the clock signal generated by the clock generation circuit is greater than a predetermined value. The delay controller outputs a signal by which delay amount in the first and second VDCs are made larger when the difference between phases of a delay clock signal output from the VDC group and of the clock signal generated by the clock generation circuit is smaller than such value.

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First Claim