Stackable microelectronic components with self-addressing scheme
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United States of America Patent
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-
Feb 25, 2003
Grant Date -
May 2, 2002
app pub date -
Jan 22, 2001
filing date -
Jul 30, 1997
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A memory device particularly useful in size-constrained electronic products, such as cardiac stimulators. To provide additional memory for such size-constrained products, memory chips are stacked one on top of another. The memory chips are configured to facilitate bonding without crossed contacts, using aligned bonding pads, vias, or castellations. Each memory chip also includes an address selection circuit that receives signals from one or more address lines to selectively enable and disable the memory chips in the stack.
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