Importance

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Abstract

A high speed memory system is disclosed. The high speed memory system remembers the active n memory rows for n banks of memory. When a memory access request for a memory address that falls within one of the active memory rows is received, the memory controller immediately responds to the memory access request. When a memory access request for a memory address that does not fall within one of the active memory rows is received, the memory controller immediately precharges and activates the desired memory address. For read operations, the memory controller responds with the data from the requested memory address after the memory has been precharged. For memory write operations, the memory controller forces the processor to halt the memory write request such that the memory controller will prepare itself by, precharging and activating the desired memory row. When the processor reissues the request, the memory controller will be prepared to immediately process the write request.

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First Claim