Method for layout and manufacture of gridless non manhattan semiconductor integrated circuits using compaction
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United States of America Patent
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Feb 25, 2003
Issued Date -
N/A
app pub date -
Oct 5, 2001
filing date -
Jun 3, 2001
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Abstract
The present invention introduces methods for implementing gridless non Manhattan architecture for integrated circuits. In one particular embodiment, an integrated circuit layout containing horizontal, vertical, and diagonal interconnect lines is first created. Next, the integrated circuit layout is then compacted. The compacting method first creates groups of horizontal and diagonal interconnect lines sorted by vertical position and groups of vertical and diagonal interconnect lines sorted by horizontal position. The two groups are then compacted in a manner that ensures that a minimum manufacturing line spacing requirement is satisfied.
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