Architecture and method for partially reconfiguring an FPGA
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United States of America Patent
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Feb 25, 2003
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app pub date -
Jul 25, 2000
filing date -
Jul 25, 2000
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Abstract
An FPGA architecture and method enables partial reconfiguration of selected configurable logic blocks (CLBs) connected to an address line without affecting other CLBs connected to the same address line. Partial reconfiguration at a memory cell resolution is achieved by manipulating the input voltages applied to the address and data lines of an FPGA so that certain memory cells are programmed while other memory cells are not programmed. In addition, partial reconfiguration at a CLB resolution can be achieved by hardwiring the FPGA to enable selection of individual CLBs for reconfiguration.
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